This invention broadly relates to a semiconductor memory device and a method of manufacturing the same.
More specifically, this invention is directed to a nonvolatile semiconductor device, such as, a flash memory.
In such a nonvolatile semiconductor device, it is becoming increasingly important to miniaturize a memory cell so as to reduce a production cost therefor.
To this end, the memory cell is generally reduced in size by reducing a design rule. However, if the design rule is simply reduced in dimension, it is also required to be reduced the dimension in a mask alignment during a production process.
Under this circumstance, the accuracy of the mask alignment (misalignment) is determined mechanically, and as a result, can not follow the speed with respect to the reduction (namely, a fine process) of the design rule. This fact prevents the miniaturization of the memory cell so as to avoid the reduction of the semiconductor memory device.
Referring to FIGS. 1 and 2, description will be hereinafter made about a related nonvolatile semiconductor memory device.
A field oxide film (device isolation region) 51 extended in a predetermined direction is deposited by the use of the known LOCOS (Local Oxidation of Silicon) method. Further, a channel region (a diffusion layer region) 52 is formed between the field oxide film 51. Thereafter, a tunnel oxide film 53 is deposited on the channel region 52.
Subsequently, a polysilicon layer containing phosphorus is formed. Thereafter, the polysilicon layer is selectively removed so as to cover at least channel region 52. Thereby, the polysilicon layer is left or remained in such a direction that the channel region 52 is extended. Thus, a floating gate 54 is formed.
After an insulating film 55 is deposited on the surface thereof, a multi-layer of WSi and polysilicon is deposited thereon. The WSi/polysilicon film is selectively removed, and serves as a plurality of word lines 56 extended in a direction which perpendicularly crosses for the channel region 52.
The insulating film 55 and the floating gate 54 are removed in a self-alignment manner with the word line 56 to form a memory cell transistor.
Next, ion implantation is carried out to form a source region 61 and a drain region 62. After an interlayer insulating film 63 is deposited, a contact 64 and a metal wiring pattern 65 are formed finally.
However, the floating gate 54 is not formed in the self-alignment manner for the channel region 52 in the related art. In consequence, when the mask displacement (misalignment) occurs for the channel region 52, a current leak (a channel leak pass) generates in the memory cell, as illustrated in FIG. 3B.
To avoid such a current leak, the memory cell has been previously designed taking the alignment deviation for the channel region 52 into consideration. Consequently, the floating gate 54 must be normally aligned for the field oxide film 51, as illustrated in FIG. 3A. As a result, the sell size is inevitably increased.
Further, the floating gate 54 are placed on the edge of the field oxide film 51 formed by the LOCOS via the tunnel oxide film 53. Thereby, the tunnel oxide film 53 is destroyed or degraded during a high-voltage writing operation or an erasing operation peculiar to the flash memory.
Thus, the floating gate 54 and the channel region 52 are not formed in the self-alignment manner in the above-mentioned related art. This fact prevents the reduction of the memory cell in comparison with the other semiconductor memory devices.
It is therefore an object of this invention to provide a semiconductor memory device which is capable of designing a fine memory cell without a mask displacement (misalignment) for a field oxide film.
According to this invention, a semiconductor memory device has a semiconductor substrate.
A field oxide film is formed to a forward taper shape on the semiconductor substrate. Further, a floating gate is formed to a reverse (inverted) taper shape between the field oxide film over the semiconductor substrate.
Herein, the forward taper shape means that side wall angle is less than 90 degrees while the reverse taper shape means that sidewall angle is more than 90 degrees
In this event, a tunnel oxide film is preferably formed between the floating gate and the semiconductor substrate.
The semiconductor substrate may comprise a p-type silicon substrate.
The field oxide film desirably has a thickness within a range between 300 nm and 500 nm.
The tunnel oxide film preferably has a thickness within a range between 8 nm and 10 nm.
Further, a word line may be formed via an insulating film on the floating gate.
For example, the semiconductor memory device is a flash memory.
More specifically, the field oxide film is deposited on the silicon substrate, and a plurality of grooves are formed so as to extend in a predetermined direction and to reach the semiconductor substrate.
Further, the side surface of the groove is formed to a forward taper shape, and the polysilicon serving as the floating gate is buried in the groove.
As mentioned above, the polysilicon serving as the floating gate is conventionally processed in accordance with the pattern of the field oxide film using the mask alignment.
In contrast, the field oxide film is deposited to the forward taper shape in this invention. Thereby, the polysilicon, which will serve as the floating gate buried between the field oxide film, is buried in the groove which has been formed in advance.
In consequence, the floating gate is formed in the self-alignment manner with the pattern of the field oxide film.
Moreover, when the floating gate is etched in the self-alignment manner during processing the word line, the etching is readily carried out without generating residue. Further, capacitance ratio as an importance device parameter of the flash memory is enhanced effectively.
Accordingly, the fine memory cell of the nonvolatile semiconductor memory device having high yield and high performance can be obtained.
Further, according to this invention, the floating gate is formed between the field oxide films processed to the forward taper shape. Thereby, the polysilocon is not readily left at the sidewall of the groove when the floating gate is etched.
Further, the floating gate has the reverse (inverted) taper structure, and thereby, has high capacitance ratio (Cox/Ctox, Ctox: tunnel oxide film capacitance, Cox: insulating (ONO) capacitance). Consequently, the flash memory is advantageous for the reading characteristic.
Moreover, the floating gate is formed in the self-alignment manner with the field oxide film. In consequence, it is unnecessary to take the mask displacement (misalignment) for the filed oxide film into account. As a result, the fine memory design becomes possible.
In addition, the floating gate does not include the LOCOS edge in comparison with the flash memory cell formed by the conventional device isolation method due to the LOCOS. Consequently, the tunnel oxide film is not readily degraded or destroyed by applying the high voltage.